Analog/Mixed-Signal Research Group
Analog / Mixed-Signal Research Group
High-Speed I/O, Data Converters, Embedded Machine Learning
AMSG NEWS
AMSG participation in the ACRC Retreat 2025 at Ein Gedi
Last week, we participated in the ACRC retreat 2025 at Ein Gedi. The ACRC retreat brings together academia and industry in the area of advanced circuits and architectures for VLSI. The main topics of this year’s retreat were AI hardware and hardware security. Dr. Nicolás Wainstein presented a talk about “Breaking AI Hardware Bottlenecks: High-Efficiency… Continue Reading AMSG participation in the ACRC Retreat 2025 at Ein Gedi
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3rd Tape Out at AMSG
Great news! We have successfully taped out a Y-flash memory array prototype using Tower 180 nm process.
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AMSG at “Worlds of Hardware” Festival
January 15th, 2025 The annual event “Worlds of Hardware” was held at the Andrew & Erna Viterbi Faculty of Electrical & Computer Engineering, Technion. It brought together people from the hardware worlds of academics, research and industry for one exciting and energetic experience. We showcased posters from our graduate students and our lab, providing attendees with… Continue Reading AMSG at “Worlds of Hardware” Festival
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2nd Tape Out at AMSG
On November 11th, we taped out our second test chip! Way to go Jeries!
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Paper accepted to IEEE T-ED
Our paper “Asymmetric and Symmetric Single-Pole Double-Throw with Improved Power Handling using Indirectly Heated Phase-Change Switches” has been accepted for publication in IEEE Transactions on Electron Devices.
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AMSG will be part of the NEMO consortium
We are thrilled to announce that AMSG will be part of the NEMO consortium, supported by the Israel Innovation Authority. NEMO will be focusing on low-power neuromorphic computing. We will be collaborating with leading research groups from academia and R&D groups from industry across Israel. Our groups will be developing two in-memory hardware accelerators for… Continue Reading AMSG will be part of the NEMO consortium
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First AMSG tape out
On January we taped out our first silicon chip on a 28 nm CMOS process! The design implements an in-memory artificial neural network accelerator. Way to go Jeries!
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