Undergrad Projects – Analog/Mixed-Signals Research Group

TechnionIIT%20English%202-lines%20reversed.png

Analog/Mixed-Signal Research Group

Analog / Mixed-Signal Research Group

High-Speed I/O, Data Converters, Embedded Machine Learning

Undergraduate Projects in AMSG

Here is a list of the open projects in our lab:

Full Peripheral Architecture Design for FeFET-Based Time-Domain Compute-in-Memory BNN Accelerator

Supervisor: Jeries Mattar

Status: Taken

RTL-to-GDS of Y-Flash-Based Time-Domain In-Memory Computing Artificial Neural Network Hardware Accelerator

Supervisor: Dima Ali Saleh

Status: Taken

FeFET-Based Time-Domain Compute-in-Memory BNN Accelerator Backend Design with MIPS/RISC-V Integration

Supervisor: Jeries Mattar

Status: Open

Design of Serial Peripheral Interface (SPI) for an Artificial Neural Network Accelerator in 180 nm CMOS

Supervisor: Dr. Nicolás Wainstein

Status: Taken

Simulator for Time-Domain Compute-in-Memory ANN Accelerators

Supervisor: Jeries Mattar

Status: Taken

Design of a Parallel Interface for an Artificial Neural Network Accelerator in 180 nm

Supervisor: Dr. Nicolás Wainstein

Status: Taken

FeFET-based Ring Oscillator in 28 nm CMOS

Supervisor: Jeries Mattar

Status: Open

Controller for FeFET-Based Time-Domain Compute-in-Memory Binary Neural Networks Accelerator

Supervisor: Jeries Mattar

Status: Taken

FeFET-Based Time-Domain Compute-in-Memory Logic Design and MAC Implementation

Supervisor: Jeries Mattar

Status: Closed

Design of Voltage-to-Time Converter for Y-Flash Based Time-Domain Compute-in-Memory ANN Accelerator

Supervisor: Jeries Mattar

Status: Taken

FeFET-Based Time-Domain Compute-in-Memory Backend Design

Supervisor: Jeries Mattar

Status: Taken

Design of Time to Digital Converter with Delay-Locked Loop

Supervisor: Jeries Mattar

Status: Taken

Analog/Mixed-Signal Research Group

Analog / Mixed-Signal Research Group

High-Speed I/O, Data Converters, Embedded Machine Learning

Undergraduate Projects in AMSG

Full Peripheral Architecture Design for FeFET-Based Time-Domain Compute-in-Memory BNN Accelerator​

FeFET-Based Time-Domain Compute-in-Memory BNN Accelerator Backend Design with MIPS/RISC-V Integration

FeFET-based Ring Oscillator in 28 nm CMOS

Full Peripheral Architecture Design for FeFET-Based Time-Domain Compute-in-Memory BNN Accelerator