Posts Tagged ‘silicon’
Jeries’ abstract accepted to IEEE NVMTS 2025
Great news! Jeries’ abstract ““A FeFET CAM-Based Time-Domain In-Memory Computing Macro with 550 ps Delay Step in 28 nm CMOS” was accepted to the IEEE Nonvolatile Memory Technology Symposium (NVMTS) to be held in Georgia Tech on September 29th. Congrats Jeries and collaborators!
Read More2nd Tape Out at AMSG
On November 11th, we taped out our second test chip! Way to go Jeries!
Read MoreFirst AMSG tape out
On January we taped out our first silicon chip on a 28 nm CMOS process! The design implements an in-memory artificial neural network accelerator. Way to go Jeries!
Read More