Analog/Mixed-Signal Research Group

Analog / Mixed-Signal Research Group

High-Speed I/O, Data Converters, Embedded Machine Learning

Data Converters & Clocking Circuits

Data converters and clock generation circuits [e.g., phase-locked loop (PLL) and (delay-locked loop (DLL)] are evolving to meet the demands of AI, 6G communications, high-speed wireline links, and low-power edge computing. In particular, wireline communication requires high-speed (>10 GS/s), medium-resolution (6–8 bit) ADCs, and high-frequency ultra-low-jitter PLLs/DLLs. Most research in high-speed ADCs focuses on time-interleaved (TI) asynchronous SAR (A-SAR) ADCs, but their loop logic limits single-channel throughput, requiring many TI channels to exceed 100 GS/s.

Time-domain ADCs (TD-ADCs), consisting of a voltage-to-time converter (VTC) and a TDC, have emerged as a promising alternative. Unlike voltage-domain approaches that rely on large passive arrays, TDCs use compact dynamic delay cells that scale well with technology. However, at high speeds, the signal amplitude of the VTC is constrained by the clock cycle, demanding subgate-delay time steps and ultra-low jitter. My research aims to push the limits of TD-ADCs by exploring novel VTC and TDC designs and hybrid ADC architectures that combine voltage and TD techniques to optimize power, speed, and resolution.

In the clock generation domain, we are investigating hybrid PLL and multiplying DLL (MDLL), ML techniques for calibration and jitter reduction. We are also working to extend previous work on high-resolution and low-locking-time DLLs.
Furthermore, we are exploring fully synthesizable TD-ADCs and MDLLs that rely only on digital standard cells for better scalability and portability.

Relevant Publications:

  1. N. Wainstein, E. Avitay, and E. Avner, "Fast-Locking and High-Resolution DLL with Binary Search and Clock Failure Detection for Wide Frequency Ranges in 3-nm FinFET CMOS," IEEE Open Journal of the Solid-State Circuits Society, 2025 (accepted for publication). (Paper)
  2. N. Wainstein and E. Avner, "A Delay-Locked Loop with Binary Search Locking and Dead Clocks Detection," Design, Technology, and Test Conference (DTTC) - Intel, 2024.
  3. N. Wainstein, E. Avitay, M. Rosenthal, and E. Avner, "Novel Clock Architecture for Ultra-Low Power DDR PHY," Design, Technology, and Test Conference (DTTC) - Intel, 2022.
  4. L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky, “Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs using a Memristive Neuromorphic Architecture,” IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 2, no. 5, pp. 396-409, October 2018. (Paper)
  5. L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky, “DIDACTIC: A Data Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 1, pp. 146-158, March 2018. (Paper)